The invention relates to an integrated digital circuit, comprising a MOS transistor of a first conductivity type whose drain is coupled to an output terminal and is connected to a first power supply terminal via a first sub-circuit, its gate being connected to a first input terminal while its source is connected to a second power supply terminal via a second sub-circuit, which second sub-circuit comprises at least one second MOS transistor of the first conductivity type, the first and the second sub-circuit being driven Via a second input terminal.
A circuit of the kind set forth is known from International patent application No. WO 86/03632 which discloses that a first transistor is connected in cascode with said second transistor in order to prevent an excessive voltage across the second transistor, which would mean that an associated high field strength at the drain of the second transistor would give rise to a real risk of so-called "hot carrier stress". The gate of the first transistor of the circuit disclosed in the cited International Patent Application receives a control voltage Vp which is equal to or smaller than the voltage +V on the first power supply terminal. In the case of a customary standard power supply voltage (for example, 5 V), a control voltage Vp equal to this positive supply voltage is not suited to transistors having channel lengths which are smaller than, for example 1 .mu.m (sub-micron), because the permissible maximum voltage beyond which "hot carrier stress" will occur across these transistors is smaller than that across transistors having greater channel lengths. In order to prevent "hot carrier stress", the control voltage Vp in said patent application should be smaller than the positive supply voltage (5 V) for sub-micron transistors. An additional circuit is required for generating control voltage Vp which is smaller than the positive power supply voltage.